1. Field of the Invention
This invention relates generally to latches and, more specifically, to a data latch that provides a full swing V.sub.pp to ground output signal. The full-swing high voltage data latch is designed using CMOS technology wherein no PMOS transistor will have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used.
2. Description of the Prior Art
Currently, in integrated circuit systems, CMOS devices are the most commonly used technology. The voltage levels used to power the CMOS devices are dependent upon the particular geometry of the CMOS devices as well as variations in the fabrication process of the CMOS devices. Most CMOS devices can operate at voltage supply levels of five (5) volts or less. With a voltage supply level of five (5) volts, a CMOS device will typically generate an output signal between the range of ground and five (5) volts.
A problem arises since many systems using CMOS technology must drive or control devices requiring input signals having a voltage magnitude greater than five (5) volts. For example, LCD displays require input signals greater than five (5) volts in order to properly function. Furthermore, memory devices like Electrical Erasable Programmable Read Only Memory (EEPROM) devices require input signals as high as twenty (20) volts or more in order to program the EEPROM device. However, CMOS devices are limited to the amount of voltage they can handle. The high voltages across the CMOS devices when used to drive LCD displays or to program EEPROM devices can cause channel, dielectric, and/or junction breakdown within the CMOS devices.
Therefore, a need existed to provide an improve high voltage data latch. The improved high voltage data latch must provide a full swing V.sub.pp to ground output signal. The full-swing high voltage data latch must use CMOS devices and be able to generate an output signal having a voltage level significantly greater than five (5) volts without suffering channel, dielectric, and/or junction breakdown within the CMOS devices. The full-swing high voltage data latch must be designed using CMOS technology wherein no PMOS transistor will have a voltage level greater than V.sub.pp /2 volts across any node. This will allow PMOS transistors with lower voltage breakdown levels to be used.